1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having a trench isolation structure and, more particularly, to a method of fabricating a semiconductor device which is designed to enhance the reliability of a gate insulating layer.
2. Discussion of Related Art
It has been substantially required to reduce the size of a device isolation region as a design rule gets decreased with very large scale integration of a semiconductor device. For that reason, LOCOS (Local Oxidation of Silicon) method is substituted by a trench isolation structure which is designed to be suitable for a small interval. The trench isolation structure is useful in reducing the size of the device isolation region because it is easy to regulate its lateral distance.
The semiconductor device having such a trench isolation structure, however, involves a problem in that it results in the depreciation of the gate insulating layer's reliability. Because the gate insulating layer is not formed well in the cross-sectional corners of the trench with the oxidation, a breakdown may occur at low voltage because of an electric field concentration in the corners of the trench when the semiconductor device is in operation.
As a solution for this problem with the trench isolation structure, a method of forming a double-layered gate insulating layer is suggested in U.S. Pat. No. 5,387,540, which is illustrated in the cross-sectional views of FIGS. 1 and 2.
In a conventional method as illustrated in FIG. 1 and FIG. 2, a first insulating layer 141 is formed on the surface of an active region 13 of a substrate 11 defined by an isolation region 12 by oxidation as shown in FIG. 1. In FIG. 2, a second insulating layer 142 is formed with CVD (Chemical Vapor Deposition), covering the corner of a trench which is not completely covered by the first insulating layer 141. With this, a gate insulating layer 14 is finally completed comprising the first and second insulating layers 141 and 142.
The isolation region 12 includes the trench, a trench liner 122 for reducing etching damage during the formation of the trench, a trench plug 123, and a channel stop region 124. The reference numeral 15 of FIG. 2 depicts a gate electrode.
The second insulating layer 142 is deposited on the first insulating layer 141 with CVD so as to cover the corner of the trench in the prior art so that it is more difficult to regulate its thickness and has a lower reliability, compared with an insulating layer formed by oxidation. Moreover, as the gate insulating layer in a very largely integrated device of 1 Giga DRAM is less than 70 .ANG. in thickness, it is hard to regulate the thickness of the gate insulating layer 14 by depositing the second insulating layer 142 on the first insulating layer 141 with CVD.